Delay-power Performance Comparison of Array Multiplier in Vlsi Design
نویسندگان
چکیده
Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, methods have been devised to minimize the delay. Two methods are common in current implementations: regular Arrays and Wallace trees. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reduction of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. These compressors make the multipliers faster as compared to the conventional design .In this paper we compare the performance of conventional Array multiplier and Array multiplier using compressor techniques with the help of Cadence Tool. Keywords-— Array multiplier, Compressors, Compressor 5:2, Compressor 6:2, Compressor 7:2.
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